A datapipe routing bridge peripheral is composed of three building blocks, a transmitter, a bridge and a receiver. The main function of the bridge component is to provide high levels of connectivity between multiple digital signal processors without paying the penalties usually associated with inter-processor connections. The individual digital signal processors are connected with unidirectional point-to-point links from a bridge terminal on one digital signal processor to a bridge terminal on another digital signal processor. Depending on the real-time comparison of the packet header information with direction identification codes (IDs) stored inside the bridge, individual data transfer packets arriving at the bridge of each digital signal processor along the way are autonomously either absorbed into the local processor or, repeated out to the next processor or, simultaneously absorbed and repeated. The bridge can function in three modes of operation, point-to-point, broadcast and inter-cell modes. The inter-cell-mode allows communications between any number of digital signal processors in groups of 32 digital signal processors per group. The datapipe bus, carrying packet streams between the bridge components of multiple digital signal processors, has built-in signals for distinguishing between control and data elements on the bus, as well as a ready line that propagates against the flow of data to stop the flow upstream of a digital signal processor node that may be temporarily backing up. The datapipe bridge improves inter-digital signal processor traffic management over existing methods in following ways:
1. It eliminates external components and reduces the number of external pins dedicated to inter-processor communication, while removing any limitations on the scope of communication, packet size and the types of connection topologies.
2. It hides the space/time complexity of moving large amounts of data between many nodes over a fixed number of links by autonomously performing all routing functions without involving the local central processing units or direct memory access units.
3. It removes any limits on how many processors can be connected together.
4. It removes any limits on how many digital signal processors can receive the same data stream as it flows around the datapipe network (broadcast/cell mode).
5. It can multiplex data and control elements on the same transfer links between digital signal processors, improving inter-processor traffic management via the ability of control elements to configure or change the path for the data elements that follow. Previous methods had to use different mechanisms to transport control and data information, negatively impacting loading/synchronization or management of on-chip peripherals that could otherwise concentrate on processing the application.
6. It includes a “ready” signal which improves inter-processor traffic management by autonomously propagating a “not ready” condition against the flow of data, to manage congestion of some transfer link segments without involvement of any chip resources. This autonomous traffic management is better than the hands-on traffic management of previous methods, because it releases valuable chip resources from having to be involved in traffic management and instead allows them to fully concentrate of the application tasks at hand.